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Design Verification

Monday, December 21, 2009. Not so "logic"al after all! I don't like "logic" type in System Verilog. It masks X's which are great to catch errors. If you define a net of type logic and read memory data into it, it changes the x in the data to 0. I know logic is good for finding multiple drivers on a bus. Also, it takes the guesswork (for some! Out of using "wire" or "reg" declaration. But this limitation of hiding X's makes it unusable for me. Subscribe to: Posts (Atom). Not so logical after all!

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Monday, December 21, 2009. Not so logical after all! I don't like logic type in System Verilog. It masks X's which are great to catch errors. If you define a net of type logic and read memory data into it, it changes the x in the data to 0. I know logic is good for finding multiple drivers on a bus. Also, it takes the guesswork (for some! Out of using wire or reg declaration. But this limitation of hiding X's makes it unusable for me. Subscribe to: Posts (Atom). Not so logical after all!

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Monday, December 21, 2009. Not so "logic"al after all! I don't like "logic" type in System Verilog. It masks X's which are great to catch errors. If you define a net of type logic and read memory data into it, it changes the x in the data to 0. I know logic is good for finding multiple drivers on a bus. Also, it takes the guesswork (for some! Out of using "wire" or "reg" declaration. But this limitation of hiding X's makes it unusable for me. Subscribe to: Posts (Atom). Not so logical after all!

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Monday, December 21, 2009. Not so "logic"al after all! I don't like "logic" type in System Verilog. It masks X's which are great to catch errors. If you define a net of type logic and read memory data into it, it changes the x in the data to 0. I know logic is good for finding multiple drivers on a bus. Also, it takes the guesswork (for some! Out of using "wire" or "reg" declaration. But this limitation of hiding X's makes it unusable for me. Subscribe to: Posts (Atom). Not so logical after all!

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Monday, December 21, 2009. Not so "logic"al after all! I don't like "logic" type in System Verilog. It masks X's which are great to catch errors. If you define a net of type logic and read memory data into it, it changes the x in the data to 0. I know logic is good for finding multiple drivers on a bus. Also, it takes the guesswork (for some! Out of using "wire" or "reg" declaration. But this limitation of hiding X's makes it unusable for me. Subscribe to: Posts (Atom). Not so logical after all!

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