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A Fossil SCM commit tool. A Tcl based build tool that includes support for building FPGA projects. A Tcl host implementation of Firmata. A small library for logging messages during testbench execution. A Tcl environment for scripting testbenches for hardware verification. An interactive tclsh that can also run commands in the background. A script for generating ASCII block diagrams from VHDL entity descriptions. A simple PCI ***** written in VHDL. A simple PCI master (and *****) written in VHDL.

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p-code | p-code.org Reviews

<META> DESCRIPTION

A Fossil SCM commit tool. A Tcl based build tool that includes support for building FPGA projects. A Tcl host implementation of Firmata. A small library for logging messages during testbench execution. A Tcl environment for scripting testbenches for hardware verification. An interactive tclsh that can also run commands in the background. A script for generating ASCII block diagrams from VHDL entity descriptions. A simple PCI ***** written in VHDL. A simple PCI master (and *****) written in VHDL.

<META> KEYWORDS

1 some projects

2 fcommit

3 ttask

4 tfirmata

5 tbmsgs

6 some older projects

7 iatclsh

8 spcis

9 spcim

10 coupons

CONTENT

Page content here

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some projects,fcommit,ttask,tfirmata,tbmsgs,some older projects,iatclsh,spcis,spcim

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p-code | p-code.org Reviews

https://p-code.org

A Fossil SCM commit tool. A Tcl based build tool that includes support for building FPGA projects. A Tcl host implementation of Firmata. A small library for logging messages during testbench execution. A Tcl environment for scripting testbenches for hardware verification. An interactive tclsh that can also run commands in the background. A script for generating ASCII block diagrams from VHDL entity descriptions. A simple PCI ***** written in VHDL. A simple PCI master (and *****) written in VHDL.

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p-code.org

1

STB

http://www.p-code.org/stb.html

STB is currently a work in progress. It's an open source project with the aim of providing an environment for scripting testbenches for verifying RTL designs, using Tcl as the testbench language. The main focus of STB is designer testing, and the design of STB is centred purely on convenience of use for an RTL designer verifying their RTL code, before the RTL code is passed over to a verification team for formal verification. STB testbenches don't need compiling, so after changing a testbench it can simp...

2

vbd

http://www.p-code.org/vbd.html

Vbd is a Tcl script that generates ASCII text block diagrams from VHDL entity descriptions. It's quite limited in the way it looks at the VHDL code, and so VHDL port declarations must be either std logic or std logic vector, and must also be declared one port per line. The generated block diagram will distinguish std logic from std logic vector, and will also group ports based on groupings in the VHDL code. For example, running. Tclsh vbd.tcl uart.vhdl. Will produce the following output:.

3

spcis - Open source PCI slave VHDL module

http://www.p-code.org/spcis.html

Spcis is a simple PCI slave VHDL module. The module consists of a slave PCI interface, a local bus interface, an asynchronous reset, and some generics for module configuration. The PCI interface signals are as follows. The spcis module has a cut down PCI slave interface which doesn't include the PCI PERR# and SERR# signals. Also the PAR signal is an output only, driven to satisfy system requirements, and is not used at any time as an input. Local bus signals are shown in the table below. Local bus data in.

4

tbmsgs

http://www.p-code.org/tbmsgs.html

Tbmsgs is a very simple library for tracking testbench progress. During a testbench run, the tbmsgs library can be used to output messages as test cases, tests and checks are executed. Messages may be redirected to a log file, and then log files may be parsed to provide a summary of all test cases run, along with any failures. My fpga gates = = - my fpga count up. Tbmsgs has four types of messages:. Running test case messages, indicating the test case running. All messages include the string '. So that a...

5

spcim: Timeline

http://www.p-code.org/spcim.fossil

Moved to fossil repo.

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A Fossil SCM commit tool. A Tcl based build tool that includes support for building FPGA projects. A Tcl host implementation of Firmata. A small library for logging messages during testbench execution. A Tcl environment for scripting testbenches for hardware verification. An interactive tclsh that can also run commands in the background. A script for generating ASCII block diagrams from VHDL entity descriptions. A simple PCI slave written in VHDL. A simple PCI master (and slave) written in VHDL.

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