kgptech.blogspot.com
My Tech Blog: October 2005
http://kgptech.blogspot.com/2005_10_01_archive.html
EBooks Link Collections, Blogger Themes, System Verilog, VMM and Many more such banalities of life. Posted by Subash 10:56 PM. Handbook of Verilog HDL. Sunburst Design : Verilog Papers. ASIC World Verilog Tutorial. Verilog HDL Quick Reference Guide. OpenCores.org : Free Open Source IP Cores for Chip Design. ASICs . The Book. Logic Design for Array Based Circuits. FFT : Fast Fourier Transform. Posted by Subash 6:38 PM. The Scientist and Engineer's Guide to Digital Signal Processing. Is exactly the name of...
dsp-world.blogspot.com
DSP WORLD: October 2008
http://dsp-world.blogspot.com/2008_10_01_archive.html
Welcome to Digital Signal Processing World! Saturday, October 18, 2008. By Swapnajit Mittra, SGI - EDN. Wednesday 21 August 2002. Swapnajit Mittra, SGI - from EDN. Designers have employed HDLs for more than a decade, using them to replace a schematic-based design methodology and to convey design ideas. Verilog and VHDL are the two most widely used HDLs for electronics design. Verilog has approximately 35,000 active designers who have completed more than 50,000 designs using the Cadence. This problem is m...
enchanterspacestudio.blogspot.com
Enchanter Space Studio: January 2012
http://enchanterspacestudio.blogspot.com/2012_01_01_archive.html
Sunday, January 15, 2012. Finite State Machines (FSM) design in Verilog. Fig 1: Moore State Machine. Fig 2: Mealy State Machine. Consider the case of a circuit to detect a pair of 1's or 0's in the single bit input. That is, input will be a series of one's and zero's. If two one's or two zero's comes one after another, output should go high. Otherwise output should be low. Fsm test ;. 16'b0101 0111 0111 0010. When reset, state becomes idle, that is 00. Next, if 1 comes, state becomes 01 and if 0 come...
