basicsofvlsi.blogspot.com
Tech Blog: September 2010
http://basicsofvlsi.blogspot.com/2010_09_01_archive.html
Wednesday, September 8, 2010. Design/Verification using Verilog/System Verilog/VHDL,ASIC/SOC , PERL, FPGA. School and Graduation -. Middle - Manager, Assistant Manager. Interview is on 11th September 2010 (Saturday) in Gurgaon. Candidates who can attend the interview on the above mentioned date need to apply only. At least 2 years of relevant design experience. Experience with digital design/Verification using Verilog/System Verilog/VHDL. (Must ). Experience with large ASIC/SOC design/verification (Must).
globalinstruments.blogspot.com
Industries Needs: DATA ANALYSIS/DATA HANDLING EQUIPMENT
http://globalinstruments.blogspot.com/2013/02/data-analysisdata-handling-equipment.html
Friday, February 15, 2013. DATA ANALYSIS/DATA HANDLING EQUIPMENT. DATA ANALYSIS/DATA HANDLING EQUIPMENT. Jhaveri House, 4th Floor. 348 Abdul Rehman Street. Mumbai 400003. India. Dipak Asharam, Partner. Surendra Jhaveri, Partner. Auro Electronics (India) Pvt Ltd. Ambala Cantt 133001. India. Uma Kant, Dir. Auroindia@sancharnet.in, auroindia@gmail.com. 1324, Shukrawar Peth. Pune 411002. India. Signals and Systems (India) Pvt Ltd. MF-7, CIPET Hostel Rd. Chennai 600097. India. No 14, Second Street. DATA ANALY...