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Semiconductor Packaging: November 2008
http://sempack.blogspot.com/2008_11_01_archive.html
The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Saturday, November 1, 2008. Intel Maintains Microprocessor Momentum in Q3. The picture was slightly different at rival Advanced Micro Devices Inc. (AMD), with the company losing share on a year-over-year basis. In the third quarter of 2008, AMD accounted for 12&#...8220;...
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Semiconductor Packaging: September 2007
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The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Sunday, September 23, 2007. To provide these necessary functions of interconnection, physical support, environmental protection and heat dissipation, the active device must be surrounded by or encased in a package. An illustrarion of this concept is presented in Figu...
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Semiconductor Packaging: Renesas Subsidiary Creates High-Temp QFN-Like Package
http://sempack.blogspot.com/2009/03/renesas-subsidiary-creates-high-temp.html
The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Monday, March 9, 2009. Renesas Subsidiary Creates High-Temp QFN-Like Package. Kenji Tsuda, Asia Contributing Editor - Semiconductor International, 2/17/2009 7:27:00 AM. Renesas Northern Japan, a subsidiary of Renesas Technology Corp. Renesas provides three types of Pro&#...
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Semiconductor Packaging: February 2007
http://sempack.blogspot.com/2007_02_01_archive.html
The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Monday, February 19, 2007. Semiconductor Packaging Goes Vertical. Stacked packaging gets more silicon in less space. Randy Frank, Contributing Editor - Design News, June 5, 2006. How PoP Stacks Up. The first PoP stack for cellphones went into production in October 2004&#...
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Semiconductor Packaging: March 2007
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The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Saturday, March 17, 2007. Silicon on Insulator (SOI). Smart Cut - The wafer bonding method is used to form the BOX, but instead of lapping off excess semiconducor (which is wasteful) a layer of hydrogen is implanted to a depth specifying the desired active layer of semic...
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Semiconductor Packaging: June 2008
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The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Saturday, June 28, 2008. Semiconductor Packaging Materials offers a variety of reel sizes. Different customers have different reeling requirements depending on the usage of the part, and the type of automated equipment being used. Larger reel sizes typically mean...Semic...
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Semiconductor Packaging: ASE Leads Gartner Packaging Market Share Ranking
http://sempack.blogspot.com/2009/03/ase-leads-gartner-packaging-market.html
The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Monday, March 9, 2009. ASE Leads Gartner Packaging Market Share Ranking. Sally Cole Johnson, Contributing Editor - Semiconductor International, 2/25/2009 9:17:00 AM. Another big part of the trouble is that capital expenditures on equipment have dried up. “Compa...Rising ...
sempack.blogspot.com
Semiconductor Packaging: March 2009
http://sempack.blogspot.com/2009_03_01_archive.html
The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. Monday, March 9, 2009. Renesas Subsidiary Creates High-Temp QFN-Like Package. Kenji Tsuda, Asia Contributing Editor - Semiconductor International, 2/17/2009 7:27:00 AM. Renesas Northern Japan, a subsidiary of Renesas Technology Corp. Renesas provides three types of Pro&#...