pdk101.com
© EDA PRIME 101
http://www.pdk101.com/EDA_related/EDA_prime.html
Commonly used EDA Tool for full custom IC design sorted by Company names. Created and maintained by Martin Chu. Last Updated on Oct 6 2012. Virtuall prototyping and Design Planning. Place and route, suitable for analog and mixed signal SOC Chip final placement and routing. Fire and Ice QXC. RC parasitic extraction commonly used in Cadence SoC encounter flow. (somewhat old tool) as of 2008. Power analysis, Voltage and IR drop, Can do some noise coupling for analog and mixed signal design. Jupiter, or Jupi...
vertigo-project.edalab.it
Vertigo - Verification and Validation of Embedded System Design Workbench
http://vertigo-project.edalab.it/files/partners.html
Provides User Requirements and Testcases. Provides tool integration Platform. EDA deployment. Provides expertise in Formal and ABV. Provides techniques and tools in SAT. Provides techniques and tools for TLM verification and coverage. Provides design and verification techniques based on Petri nets. Tallinn University of Technology. Provides techniques and tools for HLDD.
testonica.com
Clients & Partners | Testonica Lab
http://www.testonica.com/clients
Ericsson Eesti AS, Estonia. Elcoteq Tallinn AS, Estonia. GÖPEL electronic GmbH, Germany. DSE A/S, Denmark. GPV Electronics, Denmark. EP-TeQ ApS, Denmark. Nordic Test Forum, Scandinavia. ELIKO Competence Center, Estonia. ASTER Technologies, France. RIS OÜ, Estonia. CERN, Conseil Européen pour la Recherche Nucléaire, Switzerland. IBM Israel, Israel. TransEDA Systems Ltd, United Kingdom. Tallinn University of Technology, Estonia. Linköping University, Sweden. Technical University Ilmenau, Germany.
electrosofts.com
VLSI: ASIC and FPGA Links -ElectroSofts.com
http://www.electrosofts.com/links/vlsi.html
VLSI Resources and Links. Articles/ Tutorials in ElectroSofts.com. SystemC: An Introduction for beginers. Verilog design: different ways of coding. Tutorial links in ElectroSofts Directory. Http:/ www.cadence.com/. Cadence - Simulators and tools for functional verification, digital IC design and design for manufacturing. For design and verification tasks, Cadence supports Verilog. Property Specific Language (PSL). Http:/ www.synopsys.com/. Http:/ www.mentor.com/. Http:/ www.fintronic.com/. Tool for synth...
