ebooksonengineering.blogspot.com

funningboy.blogspot.com

learning plus: 六月 2014

http://funningboy.blogspot.com/2014_06_01_archive.html

ESL & SOC & Embedded World. Raspberry pi control LED on/off. Control GPIO pin 16, 18 to turn on/off led. Send remote control command to Server. 訂閱： 文章 (Atom). ASIC-System On Chip (SoC)-VLSI Design. 30001; sean chen. 35069;作，以 創用CC 姓名標示-非商業性-相同方式分享 3.0 台灣 授權條款. 37323;出。 27492;作品衍生自 funningboy.blogspot.com. 36229;出此條款範圍外的授權可於 http:/ funningboy.blogspot.com/. 26597;閱。 Awesome Inc.範本. 由 Blogger.

funningboy.blogspot.com

learning plus: 十一月 2014

http://funningboy.blogspot.com/2014_11_01_archive.html

ESL & SOC & Embedded World. Django scrapy celery redis. Pip install service identity. Brew install mongodb - with-openssl. Install 3rd part libs. Users/seanchen/tool/mongodb/mongodb-osx-x86 64-2.6.4/bin:/U. Export C FORCE ROOT=true. 訂閱： 文章 (Atom). ASIC-System On Chip (SoC)-VLSI Design. Django scrapy celery redis. 30001; sean chen. 37323;出。 27492;作品衍生自 funningboy.blogspot.com. 26597;閱。 Awesome Inc.範本. 由 Blogger.

funningboy.blogspot.com

learning plus: 六月 2013

http://funningboy.blogspot.com/2013_06_01_archive.html

ESL & SOC & Embedded World. UVM AXI BFM 1.0 release. Out of order/ inorder transactions. Each write/read phase is independent. MAX, AVG, MIN bus bandwidth. Transaction list(disassemble bus info). Define each phase delay(req to grant or each valid/ready) or drive trx out time stamp. Define each phase delay(req to grant or each valid/ready) or drive trx out time stamp. User define TRX language. Https:/ github.com/funningboy/uvm axi. Http:/ cluelogic.com/tag/vmm/UVM AGENT. Case ( recipe ). Uvm config db#( v...

funningboy.blogspot.com

learning plus: 十月 2013

http://funningboy.blogspot.com/2013_10_01_archive.html

ESL & SOC & Embedded World. Llvmpy = JIT python via llvm keynotes. A jit python interpreter via llvm. A wrapper interface between llvm c/c function calls and python interface. Wrapper c/c code to shared lib, such as pass, target, VM. Explore the shared lib to python import path. Include "dpi.h" /* c add */ int c add(int a, int b) { return a b; }. Wrapper it via c/c python extend. Register to python search path. From distutils.core import setup, Extension # ref : http:/ docs.python.org/2/exten...Http:/ do...

funningboy.blogspot.com

learning plus: 五月 2013

http://funningboy.blogspot.com/2013_05_01_archive.html

ESL & SOC & Embedded World. Xilinx ucf constrain notes. Input pad to first flip-flop groups. Internal flip-flop to flip flop groups. Out flip-flop to output pad groups. From one clock dom to another clock dom. Using async fifo to avoid the data missing issue. Req fifo.empty/fifo.full. DCM / DLL/ PLL. Slack (setup path): = (requirement - (data path - clock path. Slack (hold path): = requirement - (clock path skew uncertainty - data path). Sytemverilog virtual interface setup time hold time check. 3 collec...

funningboy.blogspot.com

learning plus: Google map test

http://funningboy.blogspot.com/p/google.html

ESL & SOC & Embedded World. Google Maps JavaScript API Example: Map Info Window. 訂閱： 文章 (Atom). ASIC-System On Chip (SoC)-VLSI Design. Django scrapy celery redis. 30001; sean chen. 35069;作，以 創用CC 姓名標示-非商業性-相同方式分享 3.0 台灣 授權條款. 37323;出。 27492;作品衍生自 funningboy.blogspot.com. 36229;出此條款範圍外的授權可於 http:/ funningboy.blogspot.com/. 26597;閱。 Awesome Inc.範本. 由 Blogger.

funningboy.blogspot.com

learning plus: 八月 2013

http://funningboy.blogspot.com/2013_08_01_archive.html

ESL & SOC & Embedded World. Verification IP support lists. Support env : systemverilog. Http:/ www.smart-dv.com/products.html. Http:/ www.truechip.net/. Support env : UVM/OVM/SystemC. Http:/ www.avery-design.com/. Python systemverilog/verilog uvm IDE (vim). Vim command line to source the uvm syntax. Source /.vim/syntax/verilog systemverilog.vim. Http:/ blog.eddie.com.tw/. It must have the target/answer in it's training phase. Using training phase to build up the. Using test phase to predict the next value.

funningboy.blogspot.com

learning plus: webrtc + image process

http://funningboy.blogspot.com/2014/05/webrtc-image-process.html

ESL & SOC & Embedded World. 訂閱： 張貼留言 (Atom). ASIC-System On Chip (SoC)-VLSI Design. 30001; sean chen. 35069;作，以 創用CC 姓名標示-非商業性-相同方式分享 3.0 台灣 授權條款. 37323;出。 27492;作品衍生自 funningboy.blogspot.com. 36229;出此條款範圍外的授權可於 http:/ funningboy.blogspot.com/. 26597;閱。 Awesome Inc.範本. 由 Blogger.

funningboy.blogspot.com

learning plus: 四月 2013

http://funningboy.blogspot.com/2013_04_01_archive.html

ESL & SOC & Embedded World. Modports(define the port type for master/slave). Master (input,output), slave(input, output). Uvm info(get full name(),"start req",UVM LOW);. Vifreq = 1b'1;. Posedge vif.clk);. Vifack) @(posedge vif.clk). Vifreq = 1'b0;. Uvm info(get full name(),"end req",UVM LOW);. Setup time, hold time, sample rate, clock rate. Http:/ learn-systemverilog.blogspot.tw/2010/07/writing-systemverilog-assertion-for.html. Transfer type, contain definition. Test env build up. Phase to phase check.