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Tuesday, August 9, 2011. How to calculate the sum of data in a queue of bits in SystemVerilog? The built-in array method sum() will return a value according to the type of queue. Flagssum() will return 0 or 1 because the type of queue is bit. To actually sum the queue data use:. Mysum = flags.sum() with (int'(item) ;. Below is an example for reference:. Mysum = flags.sum(); / this will return 0 or 1. Mysum = flags.sum() with (int'(item) ; / this will return the total value of every element. Class Rd Wr R...

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Tuesday, August 9, 2011. How to calculate the sum of data in a queue of bits in SystemVerilog? The built-in array method sum() will return a value according to the type of queue. Flagssum() will return 0 or 1 because the type of queue is bit. To actually sum the queue data use:. Mysum = flags.sum() with (int'(item) ;. Below is an example for reference:. Mysum = flags.sum(); / this will return 0 or 1. Mysum = flags.sum() with (int'(item) ; / this will return the total value of every element. Class Rd Wr R...

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Tuesday, August 9, 2011. How to calculate the sum of data in a queue of bits in SystemVerilog? The built-in array method sum() will return a value according to the type of queue. Flagssum() will return 0 or 1 because the type of queue is bit. To actually sum the queue data use:. Mysum = flags.sum() with (int'(item) ;. Below is an example for reference:. Mysum = flags.sum(); / this will return 0 or 1. Mysum = flags.sum() with (int'(item) ; / this will return the total value of every element. Class Rd Wr R...

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front-end-verification: August 2011

http://front-end-verification.blogspot.com/2011_08_01_archive.html

Tuesday, August 9, 2011. How to calculate the sum of data in a queue of bits in SystemVerilog? The built-in array method sum() will return a value according to the type of queue. Flagssum() will return 0 or 1 because the type of queue is bit. To actually sum the queue data use:. Mysum = flags.sum() with (int'(item) ;. Below is an example for reference:. Mysum = flags.sum(); / this will return 0 or 1. Mysum = flags.sum() with (int'(item) ; / this will return the total value of every element.

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front-end-verification: Virtual Prototyping

http://front-end-verification.blogspot.com/2011/05/virtual-prototyping.html

Tuesday, May 3, 2011. Following link will give you a idea about the what do you mean by Virtual Prototyping. And advantages of using this. Http:/ www.vmmcentral.org/vmartialarts/2010/10/accelerating-design-verification-with-virtual-cpu-models/. Subscribe to: Post Comments (Atom). View my complete profile. Macros to simplify the Register Write/Read Operati. Book on FPGA Based Prototyping. Picture Window template. Powered by Blogger.

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front-end-verification: April 2011

http://front-end-verification.blogspot.com/2011_04_01_archive.html

Tuesday, April 26, 2011. Killing Sequences on Sequencer Abruptly. Sometimes you may need to drive input until you see come condition or some timer expires. Once you meet that condition, you need to stop generating stimulus. The code for this scenario look like below. Wait(rtl linkup = 1);. Idles transmit.start(Sequencer);. Wait(rtl linkup = 1);. Idles transmit.start(Sequencer);. Sequencer.stop sequence();. Class idles transmit extends ovm sequence #(REQ= packet);. Bit received item done;. 2 Your vision o...

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front-end-verification: March 2011

http://front-end-verification.blogspot.com/2011_03_01_archive.html

Monday, March 14, 2011. Using the UVM 1.0 Release with Questa « Verification Horizons BLOG. Using the UVM 1.0 Release with Questa « Verification Horizons BLOG. Thursday, March 10, 2011. Comparing Signal Strength in Verilog/Systemverilog. Language doesn’t allow you directly to compare the signal strength. But you can compare strengths by converting the strings. By using the following. Macro you can achieve the required function. Define compSigValues(siga, sigb). String sigaStr, sigbStr;. The gotcha is whe...

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front-end-verification: May 2011

http://front-end-verification.blogspot.com/2011_05_01_archive.html

Thursday, May 5, 2011. You can observe the Aldec Events in above link. Macros to simplify the Register Write/Read Operations using OVM RGM Package. The Sequences or macros provided by OVM RGM can't be used inside the Testcases and those can be used in one of the RGM Sequence only. Also these macros won't allow us to write Field write/read operations. To understand this assume following structure for Register Database for small environment looks like below. The Register Database will have. REGNAME rgm reg;.

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Tuesday, August 9, 2011. How to calculate the sum of data in a queue of bits in SystemVerilog? The built-in array method sum() will return a value according to the type of queue. Flagssum() will return 0 or 1 because the type of queue is bit. To actually sum the queue data use:. Mysum = flags.sum() with (int'(item) ;. Below is an example for reference:. Mysum = flags.sum(); / this will return 0 or 1. Mysum = flags.sum() with (int'(item) ; / this will return the total value of every element. Class Rd Wr R...

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